ontrol Systems and Computers, N6, 2016, Article 4

Upr. sist. maš., 2016, Issue 6 (266), pp. 34-39.

UDC 004.274

Barkalov A.A., Doctor (Eng.), Institute of Computer Engineering and Electronics, Institute of Informatics and Electronics Zielenogorski University, ul. Podgorna, 50, Zielona Gora, 65-246, POLAND, a.barkalv@imei.uz.zgora.pl,

Titarenko L.A.,Doctor (Eng.), Professor, Institute of Computer Engineering and Electronics, Institute of Informatics and Electronics Zielenogorski University, ul. Podgorna, 50, Zielona Gora, 65-246, POLAND,

Vizor Y.E., PhD (Eng.), +38 (044) 526-25-04, V.M. Glushkov Institute of Cybernetics of National Academy of Sciences of Ukraine, Kyiv, 03187, Glushkov ave., 40, Ukraine, E-mail: yaviz@ukr.net,

Matvienko A.V., Researcher Associate, V.M. Glushkov Institute of Cybernetics of National Academy of Sciences of Ukraine, Kyiv, 03187, Glushkov ave., 40, Ukraine, +38 (044) 526-30-69, E-mail: matv@online.ua.

An Optimal State Assignment for the Combined Automation

Introduction. An offer in-process method allows to decrease the number of EMB blocks and LUT elements in the chart of the combined microprogram automat. It is arrived at due to the corresponding encryption of the states. Thus, the optimal encryption of the states is primery, allowing to decrease the number of address entrances of EMB. The optimization of LUT block is needed at violation of corresponding terms. The codes of the states can be changed without the change of code of class of K (Bi ). The codes of the states have got the specified features.
 
Purpose. The analysis of the used library showed that this method allows to get charts with one block of EMB for 82% of all examples. Thus, corresponding condition is violated in 46% of all examples. Transposition of the codes of the state allows to decrease the number of LUT elements for 60% of these examples.

Conclusion.  Further direction of researches is related to adaptation of the new features of the combined automat. It allows to decrease the number of LUT elements in the block of replacement of the logical terms as compared to  the well-known replacement methods.

 
Download full text! (In Russian)

Keywords: combined FSM, FPGA, LUT, EMB, synthesis, graph-scheme of algorithm. 

 
 1. Baranov S. Logic Synthesis for Control Automata. Dordrecht: Kluwer Acad. Publ., 1994. 312 p.
 2. DeMicheli G. Synthesis and Optimization of Digital Circuits. – New York: McGraw-Hill, 1994. – 636 p.
 3. Соловьев В.В. Проектирование цифровых схем на основе программируемых логических интегральных схем. – М.: ТЕЛЕКОМ, 2001. – 636 с.
 4. Skliyarova I.,  Sklyarov V.,  Sudnitson A.  Design of FPGA–based circuits using Hierarchical Finite State Machines. – Tallinn: TUT Press, 2012. – 240 p.
 5. Грушницкий Р.И., Мурсаев А.Х., Угрюмов Е.П. Проектирование систем с использованием микросхем
программируемой логики. – СПб: БХВ. – Петербург, 2002. – 608 с.
 6. Synthesis and Optimization of FPGA-based Systems /
V. Sklyarov, I. Skliarova, A. Barkalov et al. – Berlin: Springer, 2014. – 432 p.
 7. Cong J., Yan K. Synthesis for FPGAs with Embedded Memory Blocks, Proc. of the 2000 ACM/SIGDA 8th Int. Symp. on FPGAs, 2000. – P. 75–82.
 8. ROM–Based Finite State Machine Implementation in Low Cost FPGAs / L. Garcia–Vargas, R. Senhadji–Navarro, M. Civit–Balcells A. et al. // IEEE Int. Simp. on Industrial Electronics. – Vigo. – 2007. – P. 2342–2347.
 9. Nowicka M., Łuba T., Rawski V. FPGA–based decomposition of boolean functions: algorithms and implementations // Advanced Computer Systems, 1999. –P. 502–509.
  10. Rawski M.,  Selvaraj H.,  Łuba T. An application of functional decomposition in ROM–based FSM implementation in FPGA devices // J. of System Architecture. – 2005. – N 51(6–7). – P. 424–434.
 11. Logic Synthesis Method of Digital Circuits Designed for Implementation with Embedded Memory Blocks on FPGAs, Design of Digital Systems and Devises. LNEE 70 / M. Rawski, P. Tomaszewicz, G. Borowski et al. – Berlin: Springer, 2011. – P. 121–144.
 12. Tiwari A., Tomko K. Saving power by mapping finite state machines into embedded memory blocks in FPGAs // Proc. of Design Automation and Test in Europe. – 2004. – 2. – P. 916–921.
 13. Yang S. Logic Synthesis and optimization benchmarks user guide. Microelectronics Center of North Carolina. –1991. – 43 p.
 14. Баркалов А.А. Принципы оптимизации логической схемы микропрограммного автомата Мура // Кибернетика и системный анализ. – 1998. – № 1. – С. 65–72.  
15. Реализация схемы совмещенного автомата в базисе FPGA  / А.А. Баркалов, Я.Е. Визор, А.В. Матвиенко и др. // Комп’ютернi засоби, мережi та системи: Зб. наукових праць. – Iнститут кiбернетики iм. В.М. Глушкова НАН України. – К., 2016. – № 15. –С. 32–40.
 16. Barkalov A.,  Titarenko L.,  Kolopenczyk M. EMB-based design of Mealy FSM. – Proc. of 12th IFAC Conf. on programmable devices and embedded syst. 2013. Р. 215–220.

Received 09.04.2016